The present invention relates to a data processing apparatus for a pipeline mode system which has a plurality of storages each accessible independently, and more particularly to a data processing apparatus featuring the control of the reading of operands from plural buffer storages.
In data processing apparatus requiring high speed processing, both a pipeline system and a buffer storage system are commonly employed. In the pipeline system, the sequence of processing an instruction is divided into a plurality of steps such as instruction fetch, decoding, address translation, operand fetch, and execution. Several instructions are executed simultaneously by overlapping the execution of these steps. In the buffer storage system, high speed buffer storages are provided, in addition to the main storage, to store those instructions frequently used in the main storage and the copies of data. When a memory reference request is given, an instruction or data to be used is obtained by accessing the buffer storages.
In the data processing apparatus adopting both a pipeline system and a buffer storage system, simultaneously with the memory reference process to the buffer storage, succeeding instructions are sequentially decoded to request reading operands from the buffer storage. However, if the buffer storage is busy when a memory reference process is requested, the following process of an operand read request cannot be executed. Therefore, a means for repeating the request to read the operand becomes necessary.
Furthermore, in case of an instruction requesting two operands at the same time, such as a multi-instruction having an SS instruction format (instruction format executing the operation from the main storage to the main storage) and a vector instruction, it is necessary to access the buffer storage two times. In order to improve the efficiency of processing such an instruction, a pipeline system having one cycle pitch per one command has been proposed (e.g., Japanese Patent Examined Publication No. 47-29332), wherein the buffer storage is divided into two portions and each portion is independently accessible. The provision of two buffer storages, each being independently accessed to read the operand, however, introduces new problems such as the need to supervise the busy/free status of the buffer storages and to provide a means for repeating the request to read the operand if the buffer storage is busy. In addition, it becomes necessary to consider the sequence of processing of reading operands.